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- Low Substrate Temperature Modeling Outlook of Scaled N-Mosfet
Low Substrate Temperature Modeling Outlook of Scaled N-Mosfet
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Low substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100¿300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1
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