Complete Symbolic Simulation of SystemC Models

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In his master thesis, Vladimir Herdt presents a novel approach, called complete symbolic simulation, for a more efficient verification of much larger (non-terminating) SystemC programs. The approach combines symbolic simulation with stateful model checking and allows to verify safety properties in (cyclic) finite state spaces, by exhaustive exploration of all possible inputs and process schedulings. The state explosion problem is alleviated by integrating two complementary reduction techniques. Compared to existing approaches, the complete symbolic simulation works more efficiently, and therefore can provide correctness proofs for larger systems, which is one of the most challenging tasks, due to the ever increasing complexity.ContentsVerification of SystemsIntroduction to Formal Verification of SystemC ModelsSymbolic Model Checking with Partial Order ReductionEfficient Symbolic State Matching using State SubsumptionHeuristic Approaches for Symbolic State MatchingEvaluation of Proposed Techniques Target GroupsLecturers and Students of Computer Sciences and Electrical EngineeringHardware Designers and Verification Engineers using SystemCThe AuthorVladimir Herdt is working as Research Assistant in the Group of Computer Architecture at the University of Bremen, where he is pursuing his PhD degree.